helloI am using Arria ii gx FPGA in Nios processor.altmemphy IP and our board main clock is 50 mhzi want to know about interfacing between DDR2 clock to FPGAmy customize board connected the DDR2 clock with the differential pair pin AJ16 and AJ15.My question is about the PLL dedicated pin how to create or assign dedicated pin in my top level designThanksNome

Hi,In Quartus, you can open the Assignments > Pin Planner.For pin out you may find your board:https://www.intel.com/content/www/us/en/support/programmable/support-resources/devices/lit-dp.html#tab-blade-1-2

Hi,Was my previous answer helpful to you? Do you have any further questions?

Hello.Thanks for your reply.Not helpful .....!My simple question is: which PLL out for DDR2 differential clock do I have to use? In our case, the Arria II GX is using pin AJ16 and AJ15 for theDDR2 clock and assigning PLL C0 and FPGA main clock is 50mhz and PLL C0 100mhz DDR IP Refclk.during compilation critical warnings occurring Warning(15899): PLL"nios_cpu:inst0_nios_cpu|lms_ctr:lms_ctr_inst0|lms_ctr_ddr2_1:ddr2_1|lms_ctr_ddr2_1_controller_phy:lms_ctr_ddr2_1_controller_phy_inst|lms_ctr_ddr2_1_phy:lms_ctr_ddr2_1_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy:lms_ctr_ddr2_1_phy_alt_mem_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy_clk_reset:clk|lms_ctr_ddr2_1_phy_alt_mem_phy_pll:half_rate.pll|altpll:altpll_component|altpll_mto3:auto_generated|pll1" has parameters clk2_multiply_by and clk2_divide_by specified but port CLK[2] is not connectedhow possible assign? In SDC fileplease help usThanks

Hi,First thing you need to check your board schematics on the available pins and the exact clock pins of your device, what is your part number of your device?You need to verify the functionally of the pins in the pin out:https://www.intel.com/content/www/us/en/support/programmable/support-resources/devices/lit-dp.html#tab-blade-1-2Once that done, open Quartus, you can open the Assignments > Pin Planner, and select the specific "CLK" pins that was reported you have in your top level, and assign it accordingly in the "Location" tab in Pin Planner.Once done, you can close the Pin Planner and double check in your Assignment Editor, if done correctly you should see a green "tick" on the specific "CLK" pins that you have assigned.

Hi,Do you have further questions?

DDR2 clock from PLL out | Altera Community

19 Replies

EBERLAZARE_I_Intel
Regular Contributor
2 years ago
Hi,

Can you use this design to see the connection and use it as template for your board? You may remove other IP that you're not using and update the top level after:
https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/exm-accelerated-fir.html

Maybe you can also share your design?
EBERLAZARE_I_Intel
Regular Contributor
2 years ago
Hi,

Can you check my previous post?
EBERLAZARE_I_Intel
Regular Contributor
2 years ago
Hi,

Try use this design to see the connection and use it as template for your board. You may remove other IP that you're not using and update the top level after:
https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/exm-accelerated-fir.html

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
- nome
  Occasional Contributor
  2 years ago
  Hello
  Thanks for your comments
  I have custom board can't change any ddr2 inclock pins because its own old nios processor working excellent
  we are still facing critical warnings from pll inclk
  
  please help us
  Thanks
  nome

Forum Discussion

DDR2 clock from PLL out

19 Replies

Recent Discussions

Agilex-5 supported Transceivers

Stratix 10 fPLL is cascade source mode doesn't lock

Queries on 46.6944 Gbps PAM4 F-Tile Configuration and Loopback Testing using Agilex7

LTPI IP - any plan to support OCP LTPI Revision 1.2? (MAX 10)

Looking for example testbench for Cyclone-V Transceiver Custom_PHY IP from UG-01080-1.7