Forum Discussion
nome
Occasional Contributor
Occasional ContributorDDR2 clock from PLL out
hello I am using Arria ii gx FPGA in Nios processor.altmemphy IP and our board main clock is 50 mhz i want to know about interfacing between DDR2 clock to FPGA my customize board connected the DD...
EBERLAZARE_I_Intel
Regular Contributor
Regular ContributorHi,
Can you use this design to see the connection and use it as template for your board? You may remove other IP that you're not using and update the top level after:
Maybe you can also share your design?
