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nome's avatar
nome
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

DDR2 clock from PLL out

hello I am using Arria ii gx FPGA in Nios processor.altmemphy IP and our board main clock is 50 mhz i want to know about interfacing between DDR2 clock to FPGA my customize board connected the DD...
Memory
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


Try use this design to see the connection and use it as template for your board. You may remove other IP that you're not using and update the top level after:

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/exm-accelerated-fir.html


As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


  • nome's avatar
    nome
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago
    Hello
    Thanks for your comments
    I have custom board can't change any ddr2 inclock pins because its own old nios processor working excellent
    we are still facing critical warnings from pll inclk

    please help us
    Thanks
    nome