Forum Discussion
Occasional Contributorddr ip phy_clk timing constraint
Hello,
I am using altmemphy ip for my application.
There is phy_clk generated by this ip.
I also used for other logic to driver external device except ddr.
So, I need to define timing contraining in *.sdc file.
create_clock -name {phy_clk} -period 13.333 -waveform { 0.000 6.667 } [get_pins {??}]
Quesiton: how to fill the ?? in the sdc file
2 Replies
AdzimZM_AlteraRegular Contributor
Hello,
Maybe you can refer to this link:
https://www.intel.com/content/www/us/en/docs/programmable/683243/21-3/create-clock-create-clock.html
Regards,
Adzim
- AdzimZM_Altera
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