lipingx
Occasional Contributor
2 years agoddr ip phy_clk timing constraint
Hello,
I am using altmemphy ip for my application.
There is phy_clk generated by this ip.
I also used for other logic to driver external device except ddr.
So, I need to define timing contraining in *.sdc file.
create_clock -name {phy_clk} -period 13.333 -waveform { 0.000 6.667 } [get_pins {??}]
Quesiton: how to fill the ?? in the sdc file