Forum Discussion

lipingx's avatar
lipingx
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

ddr ip phy_clk timing constraint

Hello, I am using altmemphy ip for my application. There is phy_clk generated by this ip. I also used for other logic to driver external device except ddr. So, I need to define timing contraining...
Memory
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.