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Altera_Forum's avatar
Altera_Forum
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18 years ago

DDR IP Core Master Read Burst

Hi,

I wrote a component that does Avalon Master Read Bursts and another that does write bursts. These components are connected exclusively to Altera's DDR IP Core via Avalon. In the simulation I see that the write bursts perform well. But the read bursts return only one 32bit word every 10-20 cycles or so. Strangely the DDR controller seems to break up the burst into single reads. I want to implement the design on a Cyclone III Starterkit which is fitted with a single 16bit DDR Memory chip.

Is this the expected performance with this setup?

In my case this would be a total show stopper..

Cheers, Alex

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    No one with ideas :confused: ? Is there no one from Altera on this board?

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Have you correctly set the "maxpendingreadrequest" values of your master which does the read in the sopc builder?

    Sorry for that wrong answer! I misread your question :(
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Unfortunately this option is only for slave ports. I've been looking a bit deeper into the simulation and found that the burst component breaks up the burst into single reads to the DDR SDRAM Controller. This way every access is hit with the full latency.

    Interestingly this only happens for the read burst. The write burst is ok.

    Maybe I have to write a component that operates directly on the local interface and

    interfaces to the Avalon-Bus. And give up on Master DMA reads. This is a bit disappointing..

    Cheers, Alex
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Hello,

    the Avalon interface in general should be able to perform pipelined read bursts as required by the DDR controller. May be the component doesn't service the handshake signals as required.

    It is probably necessary to analyze operation in detail to see the point, where the continue information is delayed and the controller abandons the burst.

    Regards,

    Frank
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Yeah I think I've got it now, the Avalon Interface is a MM Slave Interface. But it does not support local read bursts greater than one :eek: . So the burst component breaks up the burst into single 32bit reads. My DDR chip is 16bit wide (Cyclone III Starter Board). Two words read from the DDR then result in one 32bit word.

    I build myself a Avalon MM Slave with the component editor. 'til now its just the interface and a counter that asserts readdatavalid burstcount times. And suddenly I see how the Avalon interconnect fabric lets my other components happily burst :p

    So the Altera DDR_DDR2 Controller is a bit limited on the Avalon Interface. Anyway I will now just use the local interface and let my Slave Component do the bursting.

    I will just break up the burst in my component and pipeline the reads as the local interface is capable of queing up to four requests. The results will just be copied to a fifo. For queing reads in my components there will be just a cmd input fifo.

    In a standalone testbench for altmemddr the altmemddr performs quite well. So

    I'll hopefully get some decent DDR performance.

    Cheers, Alex