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Altera_Forum's avatar
Altera_Forum
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18 years ago

DDR IP Core Master Read Burst

Hi, I wrote a component that does Avalon Master Read Bursts and another that does write bursts. These components are connected exclusively to Altera's DDR IP Core via Avalon. In the simulation ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Unfortunately this option is only for slave ports. I've been looking a bit deeper into the simulation and found that the burst component breaks up the burst into single reads to the DDR SDRAM Controller. This way every access is hit with the full latency.

Interestingly this only happens for the read burst. The write burst is ok.

Maybe I have to write a component that operates directly on the local interface and

interfaces to the Avalon-Bus. And give up on Master DMA reads. This is a bit disappointing..

Cheers, Alex