DDR IP Core Master Read Burst

Yeah I think I've got it now, the Avalon Interface is a MM Slave Interface. But it does not support local read bursts greater than one :eek: . So the burst component breaks up the burst into single 32bit reads. My DDR chip is 16bit wide (Cyclone III Starter Board). Two words read from the DDR then result in one 32bit word.

I build myself a Avalon MM Slave with the component editor. 'til now its just the interface and a counter that asserts readdatavalid burstcount times. And suddenly I see how the Avalon interconnect fabric lets my other components happily burst :p

So the Altera DDR_DDR2 Controller is a bit limited on the Avalon Interface. Anyway I will now just use the local interface and let my Slave Component do the bursting.

I will just break up the burst in my component and pipeline the reads as the local interface is capable of queing up to four requests. The results will just be copied to a fifo. For queing reads in my components there will be just a cmd input fifo.

In a standalone testbench for altmemddr the altmemddr performs quite well. So

I'll hopefully get some decent DDR performance.

Cheers, Alex