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Altera_Forum
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18 years ago

DDR IP Core Master Read Burst

Hi, I wrote a component that does Avalon Master Read Bursts and another that does write bursts. These components are connected exclusively to Altera's DDR IP Core via Avalon. In the simulation ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hello,

the Avalon interface in general should be able to perform pipelined read bursts as required by the DDR controller. May be the component doesn't service the handshake signals as required.

It is probably necessary to analyze operation in detail to see the point, where the continue information is delayed and the controller abandons the burst.

Regards,

Frank