DCFIFO simultaneous read and write problem

I'm having problems with the dcfifo IP block when simulating in modelSim.

I'm using the same clock on both the read and writes ports, I'm only using the dual clock FIFO as I want to feed data in with 32bit width and read out 16bit width.

The error occurs when there is a write and read on the same clock cycle.

The fifo is configured as:

intended_device_familt => "Cyclone IV GX",

lpm_numwords => 1024,

lpm_showahead => "ON",

lpm_type => "dcfifo_mixed_widths",

lpm_width => 32,

lpm_widthu => 10,

lpm_widthu_r => 12,

lpm_width_r => 16,

overflow_checking => "ON",

rdsync_delaypipe => 3,

read_aclr_synch => "OFF",

underflow_checking => "ON",

use_eab => "ON",

write_aclr_synch => "ON",

wrsync_delaypipe => 3

My testbench runs OK until there happens to be a clock cycle where wrreq and edreq are both '1'. The value written here is lost along with many subsequent writes. Data is still read out OK until we get to reading the value where the simultaneous access occurred, and then we just get "000...." out.

The level of the FIFO is 1931 as reported on the rdusedw port. At the time the simultaneous access occurs my test bench is reading data faster than it's writing. So although the FIFO is quite full it isn't overflowing.

I have tried putting in a line of code to delay the write clock by 1 simulation delta cycle (writeClock <= clock) and even delaying the write clock (writeClock <= clock after 1nS), but this has had no effect.

I haven't tried running this design on hardware yet, so can't say if this is just a simulation error or not, but I can't believe that this FIFO would fail in this way.

Any ideas?

Mark