DCFIFO simultaneous read and write problem

This does sound a bit odd, and I hope it's just a simulation issue.

One bug I have noticed, is that your lpm_widthu_r is wrong. It should be 11, not 12, as the read port only has 2048 locations (unless you're trying to see the depth when it's full, but Im not sure if the internal logic will work like that).

Does the FIFO report the data is valid? was the wrfull flag high when you wrote the failing value in?

Try stopping the write at the point of the failing data, is the "0000..." value marked as not empty?

I did find a bug a long long time ago (about 7 years ago) with the DC fifo. I had a similar config to you (but ip and op widths were the same) and the read and write clocks were the same clock frequency but from different sources (so there were some PPM differences). Every now and again the read side pointer would reset back to 0 for no apparent reason, and as the data was video data, you would see the left side of the specific line repeated on the rhs of the screen. This was on a Cyclone 1. Never a problem with a sim, just an implementation glitch (and took a long while to find the source.)