DCFIFO simultaneous read and write problem

Thanks Tricky,

I have the lpm_widthu_r set to 12 so that it doesn't roll round to 0 when full. There is an option in the Mega Wizard that allows you to add an extra MSB to the level.

My system has an external bus that reads the FIFO along with a number of status and control registers. So that the level reports correctly I need the extra bit. In the past when I've used the single clock fifo I've just appended the full flag. Because of the pipeline in the dual clock FIFO the I couldn't do this here, so I manually added one bit to the lpm_widthu_r.

My design doesn't use the wrusedw port, so I didn't think to change the lpm_widthu generic.

Setting lmp_width_u to 11 has fixed my design! :)

Seems that if you add the extra MSBit to the "used words" ports you need to do it on both.:confused:

Mark