Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Cyclone V SDI ii IP CORE,how to use altera-modelsim to simulate?

Hi,

Could you help me for three questions about Cyclone V SDI ii IP core?

First question:

I use two SDI ii cores, one for TX and one for RX, pattern gen ---- SDI ii TX ---- SDI ii RX.

The SDI ii core generate TX and RX files(xx_rx_sim, xx_tx_sim) are the same name sdi_ii_0001, so I use modelsim to simulate error.

How to resolve this?

Second question:

SDI v14.0 IP CORE can use for Quartus 14.0? I use it same to sdi ii core ,but sdi v14.0 core work Abnormally.

Third queston:

SDI ii demo design -- sdi_ii_reconfig_logic -- Transceiver Reconfiguration Controller Streamer Module Registers mode 1,direct write.

assign override_hd_data = ((FAMILY == "Stratix V") | (FAMILY == "Arria V GZ")) ? ({readdata[31:16],

((std_select[0] && ~std_select[1]) ? 4'h3: 4'h5),

((std_select[0] && ~std_select[1]) ? 4'ha: 4'h5),

readdata[7:5], 1'b0, readdata[3:0]}) :

({readdata[31:16], 2'b00,

((std_select[0] && !std_select[1]) ? 4'h3: 4'h5),

((std_select[0] && !std_select[1]) ? 4'ha: 4'h5),

readdata[5:4],1'b0,readdata[2:0]});

why ? I don't found it in the sdi_ii core use guide.pdf and xcvr_use_guide.pdf.

Thank for your help.

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Third queston:

    SDI ii demo design -- sdi_ii_reconfig_logic -- Transceiver Reconfiguration Controller Streamer Module Registers mode 1,direct write.

    assign override_hd_data = ((FAMILY == "Stratix V") | (FAMILY == "Arria V GZ")) ? ({readdata[31:16],

    ((std_select[0] && ~std_select[1]) ? 4'h3: 4'h5),

    ((std_select[0] && ~std_select[1]) ? 4'ha: 4'h5),

    readdata[7:5], 1'b0, readdata[3:0]}) :

    ({readdata[31:16], 2'b00,

    ((std_select[0] && !std_select[1]) ? 4'h3: 4'h5),

    ((std_select[0] && !std_select[1]) ? 4'ha: 4'h5),

    readdata[5:4],1'b0,readdata[2:0]});

    why ? I don't found it in the sdi_ii core use guide.pdf and xcvr_use_guide.pdf.

    Thank for your help.

    --- Quote End ---

    For the direct write reconfiguration, user will need to create own logic to control the read and write of the required register values. Since this is user created logic, I believe this is why you could not find it in the user guide.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    --- Quote Start ---

    Hi,

    Could you help me for three questions about Cyclone V SDI ii IP core?

    First question:

    I use two SDI ii cores, one for TX and one for RX, pattern gen ---- SDI ii TX ---- SDI ii RX.

    The SDI ii core generate TX and RX files(xx_rx_sim, xx_tx_sim) are the same name sdi_ii_0001, so I use modelsim to simulate error.

    How to resolve this?

    Second question:

    SDI v14.0 IP CORE can use for Quartus 14.0? I use it same to sdi ii core ,but sdi v14.0 core work Abnormally.

    --- Quote End ---

    Q1: Is it that you are observing the module name for both TX and RX instances are the same? Probably you can try to change the module name and see. You can also try to use duplex mode to see if helps.

    Q2: SDI v14.0 should be targeted for Quartus II 14.0. What is the abnormal observation with this core? Do you observe the same if using the latest Quartus II 15.0?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Thanks for bfkstimchan and nic_@ replies.

    Q1: The module name for both TX and RX instances are different, so I think this is a bug or I didn't use it correctly.

    My design only need RX,so I use TX to simulate it.

    Q2: I use TX SDI ii ip,it outputs tx is okay,but using sdi ip it outputs wrong.

    Q3: I know it's user created logic, I find the data register[31:0] phy address is 7'h3C. But I don't know every bit define for data register[31:0].
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Q1 :The module name for both TX and RX instances are different. My design only use RX,so I want to use TX to simulate it .

    Q3:I find the data register[31:0] for phy address 7'h3c, but I don't find the every bit define for the data register[31:0].
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    If you are using V-series devices, then I would suggest you to use SDI II IP core instead of SDI I.

    For the SDI TX and SDI RX simulation, you should compile the sdi_ii_0001 in difference library folder.

    For evaluation purpose, you can just use duplex, I don't see there is a problem.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Now I use duplex.

    Setting the duplex for HD SDI, it work okay.

    But setting the dulpex for dual standard,it need to add reconfig_logic.v to control the reconfiguration , it outputs rx errorly. I use the reconfig_logic.v from the demo design.

    Why the reconfig_busy and sdi_start_reconfig are the picture as follows?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Setting the sdi dulpex for dual standard also can work now,through adding channel/pll reconfiguration.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Hi yuanmu0908,

    Glad to hear that you have managed to get your SDI duplex working now.