Cyclone V SDI ii IP CORE,how to use altera-modelsim to simulate?

Third queston:

SDI ii demo design -- sdi_ii_reconfig_logic -- Transceiver Reconfiguration Controller Streamer Module Registers mode 1,direct write.

assign override_hd_data = ((FAMILY == "Stratix V") | (FAMILY == "Arria V GZ")) ? ({readdata[31:16],

((std_select[0] && ~std_select[1]) ? 4'h3: 4'h5),

((std_select[0] && ~std_select[1]) ? 4'ha: 4'h5),

readdata[7:5], 1'b0, readdata[3:0]}) :

({readdata[31:16], 2'b00,

((std_select[0] && !std_select[1]) ? 4'h3: 4'h5),

((std_select[0] && !std_select[1]) ? 4'ha: 4'h5),

readdata[5:4],1'b0,readdata[2:0]});

why ? I don't found it in the sdi_ii core use guide.pdf and xcvr_use_guide.pdf.

Thank for your help.

--- Quote End ---

For the direct write reconfiguration, user will need to create own logic to control the read and write of the required register values. Since this is user created logic, I believe this is why you could not find it in the user guide.