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Altera_Forum
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16 years ago

Cyclone III DDR2 CK/CK# pin placement

Hi, I am connecting two 16-bit DDR2 devices (32-bits total) to an EP3C55F484. I am connecting the devices to the bottom banks (bank 3 and 4). The Cyclone III databook states that the CK/CK# ...
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Altera_Forum
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16 years ago

Hi Kevin,

Thanks! After sending the message I realized that row/column could not refer to BGA pins since not all packages are BGA! So I guessed it had to do with the die, but I would not have figured it without your pointer. Looking at the Pad View, I see my CK/CK# clock pair in a group of three pins, where the third pin seems to be unused in my package (probably used in the larger BGA). I guess then that the requirement means that none of the other pins in a group containing the CK/CK# pins are allowed to be DQ pins?

Regards,

Niki