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Altera_Forum
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15 years ago

Cyclone III DDR2 CK/CK# pin placement

Hi, I am connecting two 16-bit DDR2 devices (32-bits total) to an EP3C55F484. I am connecting the devices to the bottom banks (bank 3 and 4). The Cyclone III databook states that the CK/CK# ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

I have never used DDR2 memory with a Cyclone III so I am not sure exactly what the requirements are. However, while working with other IP I have learned that when the documents are referring to row or column I/O, it is not referring to the rows and columns of the BGA pin matrix, but the internal layout of the actual chip die.

To aid in placing pins which have special requirements like this, I find it is easier to open the "Pad View" in the Pin Planner. When you click a pin in either view, the pin will also be highlighted in the opposite view. The pins along the top and bottom are the row I/Os, and the pins to the left and right are the column I/Os.