Hi Wincent,
For the FPGA, its a custom design based the example project. Basically just the PCIe Hard IP and our custom IP is connected through the Bar2 avalon MM bus.
It's not stuck at Detect.Active, it goes through Polling.Compliance then link down.
I looked at turning on/off termination on refclk but it appears internal termination is turned on by default for the Cyclone10Gx.
We have 2 setups, a full Raspberry Pi 5 and a CM5. Then we use a converter/breakout board for both to convert the Pi's PCIe interface to a standard PCIe x1 slot. Link below:
Amazon.com: GeeekPi P02 PCIe Slot for Raspberry Pi 5, Pi 5's PCIe to PCIe x1 Slot, Support Network Interface Card : Electronics
Note that we have an older PCIe card design which uses NXP's PX1011B PCIe X1 PHY and this gets recognized by Windows as well as the Raspberry Pi on the same hardware setup.
Thanks!