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mattsqp
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4 months ago

Cyclone 10 GX Dev Kit: IOPLL not locking when using CvP mode

Hi everyone, I'm working with a simple CvP-based design on the Cyclone 10 GX Development Kit. My design is based on the official CvP example design, with a small modification: I've added an IOPLL th...
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mattsqp
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4 months ago

Hi Farabi,

Thanks for your help. I believe I’ve identified the root of the problem. I noticed that the Cyclone 10 GX FPGA series only supports CvP initialization mode (one-time configuration via PCIe after power-up), but not the CvP Update mode (reconfiguration during runtime).

This limitation seems to be a plausible explanation for the system behavior I’ve been observing. I found this information mentioned here:
https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Cyclone-10-GX-CvP/m-p/1326978#M21253

What do you think?

Also, I’ve been wondering how to verify that a peripheral image *.periph.jic and a core image *.core.rbf are compatible with each other.

Is there a tool in Quartus Prime that can help with this?
As far as I can tell, a simple binary comparison of the peripheral images from two different FPGA builds doesn’t seem sufficient to check compatibility.

Thank you in advanced