Cyclone 10 GX Dev Kit: IOPLL not locking when using CvP mode

Hello,

From your statement :

1- After power up, programming the *.core.rbf works fine- meaning IOPLL locks.

2- Reprogramming the same *.core.rbf without power cycle- IOPLL wont lock.

In your design- your state machine pll_ctrl_state_r controlling the syspll_rst based on lock status and timeout counters. PLL is reset (syspll_rst = 1) when state machine enter pll_reset.

After power up, state machine wait for PLL to lock. If it doesnt lock- SYSPLL_TIMEOUT_C asserts a reset. However, after programming, PLL might not received proper reset signal because pcie_perstn remains high.

You may need to add an explicit PLL reset after CvP re-programming.

1- Try to add logic to assert syspll_rst for few cycles after CvP reprogamming completed.

2- Use a signal to detect CvP completion and trigger short reset pulse.

regards,

Farabi