CXL Type 3 + AXI Reg slice causing system deadlock

Hi Rong,

Yes, exactly. In essence, we want to perform some manipulation to the AR request. Specifically, we would like to filter out some read requests, and reply with dummy data. However, to implement this demux/interconnect, we need some registers between the connection of cxlip2iafu and iafu2mc, to have time to do our logic. However, whenever I add a register for the AR signal, it seems like we get a bus deadlock. I'm taking care to ensure that we're doing a valid/ready handshake on both sides of afu_top when appropriate, so it shouldn't have any correctness issues.

I'm worried that there's a bug somewhere in the CXLIP or in the AXI to AVMM to MC path, that is only getting exposed when we buffer the AR requests. I think next I will try an open source AXI firewall, or a verification IP, and see if that reports errors.