Hai, I am using Qsys to integrate all the custom IPs developed.I am using NiosII SBT to access the IPs. When i add a new IP to Qsys and try to access from Nios,its not working.Does anyone have these kind of probs? By adding a custom IP ,the nios ii goes to the reset state.who is actually resetting the nios?? I have seen that my IPs timing simulation works fine. Please help in this.

I do not know what your Qsys condition. but those are my guess. - who is resetting the nios. it must be you. did you make sure reset pin of Qsys input. if you leave it open which means it is resetting because Qsys reset pin is active low. - Custom IP is not working. how do you check Custom IP? I think you can not check Custom IP as long as Qsys is being reset.

What errors/failures are you seeing and where? And what is in your system?

Hai all, Thanks for your replies.I have removed the custom IPs and started building the Qsys with only PIO's. Now I have added upto 45 no: of PIO's in the Qsys and generated the system.After that i have build the quartus project with the generated Qsys. Then i used Nios SBT for debugging.During the debug for the helloworld.c program itself it get resetted.What can be the reason for the reset? I have ensured in the hardware that the pin which is assigned as the reset pin of the nios is active high .Is there any limitation in the no: of PIO's which can be used in a Qsys? I am using Cyclone IV EP4CE22E22I7 FPGA based digital controller card for the development.If i reduce the no: of PIO's it is working fine. Please see the attached Qsys image also. Need help in sorting this issue....

hello manjurgl. do you think reset is active high? normally reset pin of NiosII ( I mean Qsys ) is active low. if you insist it is active high, that is fine. could you upload your Qsys file on this page? I think I can help you.

Hai Akira, I have uploaded the Qsys file for your reference. The reset is active high? Please help

Custom IP problem | Altera Community

15 Replies

Altera_Forum
Honored Contributor
10 years ago
What board are you using?
Altera_Forum
Honored Contributor
10 years ago
--- Quote Start ---
What board are you using?
--- Quote End ---

this is a custom made development board for Cyclone IV series.
Altera_Forum
Honored Contributor
10 years ago
--- Quote Start ---
this is a custom made development board for Cyclone IV series.
--- Quote End ---

You may want to consider getting a sanity check on your Quartus/Qsys/NIOS projects using a commercial board.

On your custom board, you need to check all of the usual things whenever you build a new board (power, clock, etc.) Your symptom sounds a lot like the FPGA itself is resetting or reconfiguring, possibly a board/design defect.
Altera_Forum
Honored Contributor
10 years ago
Sir,
I have check the power level and the clock .That seems to be ok. Also with normal schematic file quartus project i am able to run the program in FPGA.But when i try to use the Nios,then only i am getting all these probs.
If i am using the PIO's as output only.Then i am able to work with the project.But if i configure them as bidirectional and set its direction as output,then only its creating the problem.
Altera_Forum
Honored Contributor
10 years ago
Try single stepping through your software and watch relevant pins/PIO's in SignalTap to isolate your issue. For example, configure SignalTap to watch all your resets, all your PIO's and their Avalon-MM ports to watch the NIOS write something to them and cause the reset to occur.

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Custom IP problem

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