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Dhiraj's avatar
Dhiraj
Icon for New Contributor rankNew Contributor
10 days ago

Constraints not being picked for DCFIFO

Hi,

I am having various DCFIFOs in my design. I have applied constraints according to the ug_fifo. Attaching link for the reference

https://faculty-web.msoe.edu/johnsontimoj/EE3921/files3921/ug_fifo.pdf

In the DRC report, I am getting a violation of CDC-50007 which shows CDC bus with insufficient constraints and it is showing set_max_skew and set_data_delay are violated. This issue is not coming up for all the DCFIFOs in the design. 

The violations are there in the path of the

  1. delayed_wrptr_g[*] to rs_dgwp|dffpipe*|dffe and  
  2. rdptr[*] to ws_dgrp[*] |dffpipe*|dffe.

In the same DCFIFO, violation is coming only on either wr_ptr or rd_ptr. Could you suggest why this constraint is not being picked in some selected FIFOs and only in either wr / rd paths?

set_data_delay is not prescribed as per the ug_fifo. 

Other Ips

2 Replies

  • KennyT_altera's avatar
    KennyT_altera
    Icon for Super Contributor rankSuper Contributor
    3 days ago

    Forget to mention, if your inputs are tied to constant values (VCC/GND), it will also be optimized away. 

  • KennyT_altera's avatar
    KennyT_altera
    Icon for Super Contributor rankSuper Contributor
    3 days ago

     

    Usually, this happens because Quartus synthesis has optimized away some of the registers.

    Can you check the .syn.rpt file to see if the registers were optimized away? This could be why the SDC constraint cannot be applied. Typically, this issue is caused by a dangling connection.

     

    Please check the report text file instead of relying on the GUI. Sometimes, many nodes are optimized away and may not be displayed in the GUI.