Forum Discussion
Occasional ContributorConfigurable transceiver enable
My understanding of "board‑level transceiver parameters are static at power‑up", implied they are compile‑time only. In practice, changing these parameters would require IP regeneration and a full FPGA recompilation, rather than being something that can be altered dynamically at runtime (i.e., they behave similarly to localparam settings).
With that in mind, let me rephrase my understanding of a possible implementation approach:
- Only 2 channels would be active in normal operation.
- The remaining channels would be treated as unused channels
- Only 1 bitstream
Based on the transceiver reset architecture described in the Cyclone 10 GX Transceiver PHY User Guide, you may want to consider this conceptual approach to instantiate a 4‑channel transceiver, and control which channel is active using the four independent reset ports per channel:
- tx_analogreset
- tx_digitalreset
- rx_analogreset
- rx_digitalreset
For the unused channels, the handling would be:
- Assert TX analog reset
- Assert RX analog reset
- Keep TX and RX digital reset asserted as well
This would prevent the unused channels from calibrating, transmitting, or receiving data, while keeping the configuration static and avoiding any runtime reconfiguration complexity.
Frequent ContributorHow about compiling two separate bitstreams; it would be a clean solution since the board parameter is static at power‑up and there is no requirement to switch channel groups at runtime. Each bitstream instantiates only two transceiver channels, using the Raw (Native) PHY, all operating at the same line rate and reference clock. For each build, the fitter simply needs to be rerun with placement constrained to either channels 1–2 or channels 3–4.
Occasional ContributorWe do not want to maintain two compiled images, then we need to keep track of which board has which image. We want all the boards to have the same image and that they detect their configuration at run-time only.
- JonWay_altera
My understanding of "board‑level transceiver parameters are static at power‑up", implied they are compile‑time only. In practice, changing these parameters would require IP regeneration and a full FPGA recompilation, rather than being something that can be altered dynamically at runtime (i.e., they behave similarly to localparam settings).
With that in mind, let me rephrase my understanding of a possible implementation approach:
- Only 2 channels would be active in normal operation.
- The remaining channels would be treated as unused channels
- Only 1 bitstream
Based on the transceiver reset architecture described in the Cyclone 10 GX Transceiver PHY User Guide, you may want to consider this conceptual approach to instantiate a 4‑channel transceiver, and control which channel is active using the four independent reset ports per channel:
- tx_analogreset
- tx_digitalreset
- rx_analogreset
- rx_digitalreset
For the unused channels, the handling would be:
- Assert TX analog reset
- Assert RX analog reset
- Keep TX and RX digital reset asserted as well
This would prevent the unused channels from calibrating, transmitting, or receiving data, while keeping the configuration static and avoiding any runtime reconfiguration complexity.
- JPrig
Sorry, I misunderstood then. My answer was for our custom board-level parameter which defines which channels to activate. Thank you for your reply. I think it answers my question.
- JonWay_altera
No worries. I am glad it helped. I will close this case then.
