Clocked Video Output slave control not functioning

Hello,

Finally some good news! The FR reader is working properly after a lot of days of hard labour. The design is added as an attachment. I made a few changes:

-The FR outputs a parallel output

-Added a Color Plane Sequencer (Parallel to Serial)

-The CVO takes a serial input, and added a control port

I only had to activate the CVO in eclipse, to make it work. So the main system is the same as the picture viewer, but now build with the VIP suite.

FR = SGDMA (parallel data)

Data conversion (parallel => serial)

CVO = synced video output (serial data)

Some things I'm still not 100% sure about:

If the FR outputs 3 pixel parallel data at a 100MHz, and the color plane sequencer uses the same clock but outputs 3 pixels as serial data. This means (in my opninion) that the Color plane sequencer needs three clocks to output one complete pixel but he get's one pixel in every clock. For my simle mind this mathematics doesn't match, it got's much more data in then it can get out. Can anyone explain? Thanks :cool:

Any comments always welcome!

Best,

Hans

Edit: I'm sorry I edited the directory names (for my archive) in the Zip file, therefor you get some makefile errors, those can be easily solved by creating a complete new "hellow orld" template and paste the contents of my hello world.c file

Very nice, I just tried it and works well. Only thing you have got to do is, to switch the linker to work with the ssram instead of the ddr_sdram and switch the exceptions to ssram in the BSP-Editor if you work with a new project.

Nice work, I will have to take a closer look how you have done it when I have got some spare time. Will implement this in another project.

Good luck with your further projects Hans! That was a nice teamwork.

Thanks, but I must say we did it together. Next step is adding a Alpha blender and a few more frame readers. After that I will try to implement Linux on the neek with use of the LCD.

The reason you have to create a new bsp file is because of the directory names I've changed (had to do it myself as well) Sorry for that!

I'll keep you posted!

Good luck with your projects as well!

Ciao

Hans ;)

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If the FR outputs 3 pixel parallel data at a 100MHz, and the color plane sequencer uses the same clock but outputs 3 pixels as serial data. This means (in my opninion) that the Color plane sequencer needs three clocks to output one complete pixel but he get's one pixel in every clock. For my simle mind this mathematics doesn't match, it got's much more data in then it can get out. Can anyone explain? Thanks :cool:

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The Color Plane Sequencer will limit the rate of the FR by applying backpressure. The CPS will only raise its ready signal 1 in 3 cycles, which stalls the Frame Reader. This ensures that the CPS only gets 1 pixel every 3 clock cycles.

Gareth.

Thanks,

This is a clear explenation!

Best,

Hans