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If the FR outputs 3 pixel parallel data at a 100MHz, and the color plane sequencer uses the same clock but outputs 3 pixels as serial data. This means (in my opninion) that the Color plane sequencer needs three clocks to output one complete pixel but he get's one pixel in every clock. For my simle mind this mathematics doesn't match, it got's much more data in then it can get out. Can anyone explain? Thanks :cool:
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The Color Plane Sequencer will limit the rate of the FR by applying backpressure. The CPS will only raise its ready signal 1 in 3 cycles, which stalls the Frame Reader. This ensures that the CPS only gets 1 pixel every 3 clock cycles.
Gareth.
Honored Contributor
