UTech
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6 years agoClock source IP is not generating the frequency provided in "clock frequency" parameter of the IP.
I'm using "Clock Source" IP provided by Altera in the QSYS. I gave 250MHz in "clock frequency" parameter, but it is providing only 100MHz from its output Clock interface. I confirmed it using Signal tap logic analyzer by sampling the clock at double its frequency (based on Nyquest theorem). My question is, why Clock source IP is not able to provide the frequency I gave in Clock frequency parameter, is their something I'm missing out while generation?
Technical Details:
FPGA : Stratix V
Part Name : 5sgxea7k2f40c2
FPGA Board : Bittware S5-PCIe-HQ
Clock pin : PIN_J23 (S5CLK16_P)
IP : Clock Source (Author : Altera Corporation, Version : 15.1)
Software : Quartus Prime Standard Edition 15.1