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UTech
New Contributor
New ContributorClock source IP is not generating the frequency provided in "clock frequency" parameter of the IP.
I'm using "Clock Source" IP provided by Altera in the QSYS. I gave 250MHz in "clock frequency" parameter, but it is providing only 100MHz from its output Clock interface. I confirmed it using Signal ...
sstrell
Super Contributor
Super ContributorYou could build your own logic to do it, but the easiest way is to simply use a PLL.
#iwork4intel
