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UTech
New Contributor
New ContributorClock source IP is not generating the frequency provided in "clock frequency" parameter of the IP.
I'm using "Clock Source" IP provided by Altera in the QSYS. I gave 250MHz in "clock frequency" parameter, but it is providing only 100MHz from its output Clock interface. I confirmed it using Signal ...
sstrell
Super Contributor
Super ContributorThe Clock Source component is just for distributing a clock to the rest of the system design. It does not generate or change an incoming clock. The parameter value you mention is just for timing constraint purposes. What clock are you providing to the Platform Design system? If you want it to be 250 MHz, you have to generate it from an outside source, like a PLL.
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