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Altera_Forum's avatar
Altera_Forum
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9 years ago

Clock_Derivered Bock Problem

Hi, I'm trying to implement a design at a sampling rate lower than the clock frequency.

So i implement this by a Clock_Derivered Block.

I'm using a Altera Cyclone® IV EP4CE22F17C6N FPGA.

The main clock i'm assinging it to PIN_R8 as said in the DE0_Nano_User_Manual.

The circuit is in the image attached.

In CLK_LOW parameters i ticked "Export As OutPut Pin".

Now the problem is that i would like to view this clock with the oscilloscope but i don't know where does this block export the clock to....neither if i have to assign the pin or how to assing this OutPut Pin.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    I solved it.

    The Clock_Derivered Block needs an input of the crystal and on that board we only have an 50Mhz crystal source at PIN_R8. I used an DSP Builder Incrementor Block and a bus splitter for the Clock_Derivered Block and assigned to it.