Altera_Forum
Honored Contributor
11 years agoCan't Simulate NCO IP core
Hello All.
I've run into a problem simulating the altera NCO IP core in ModelSim Altera. I've created an instantiation with the correct parameters and Quartus can compile it fine (there are a few warnings but nothing major). I've then attempted to simulate my design and I keep running into the same error. ModelSim brings up a warning about only being able to use a single HDL language (in Altera form) and then an error that it can't find an entity. The entity that is missing has a name of [my instantiation]_ts. I've been through the files created by core gen and I can only see this as A Verilog Module in a .v file but I can't find a VHDL equivalent. As much as Verlog is my native language I've been forced to use VHDL. I've confirmed that the simulation settings in core gen are set to give me VHDL output. I've re-run the generate just to be safe but with no luck. Does anyone know of a solution to this, as I'm stuck without it? I'm using a slightly old version of Quartus (13) simply because I know and trust it for the platform I'm targeting. If an upgrade will defiantly cure the problem then I'm happy to do so, but as I'm weeks away from delivery I don't want to mess things about if I don't have to. Regards, and thanks in advance Russell