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Altera_Forum's avatar
Altera_Forum
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14 years ago

Can't download to FPGA hardware

There is a FFT IP core in my design. I can simulate and compile my design in simulink and Quartus II (9.1) successfully.

But when I try to download the design from PC to hardware, there are some Warnings, such as "Design contains one or more time-limited OpenCore Plus cores that will not work after the hardware evaluation time expires".

At last there is an "error: Can't communicate with device. Device will stop

functioning when it reaches its non-tethered mode timeout limit."

My design can't download to hardware at all!

Could any friends tell me the reason?:confused::confused:

PS: From the informations of IP, it should "Program a device and verify the

design in hardware" with the time-limited file. Why couldn't my design?:(

I have used another PC to try the same design, and also the same result...

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    These are some common problems initailly.Restart ur PC and try again check all connections ingore warning.But you can try it surely.There are more threads on it.Read it there.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    These are some common problems initailly.Restart ur PC and try again check all connections ingore warning.But you can try it surely.There are more threads on it.Read it there.

    --- Quote End ---

    Thank you very much for your reply！！!

    But when this error occurred, I had to try to restart all the project, recompile the Simulink and Quartus Project, or use another PC. All the methods were failed. I have tried more than one week.

    Strangely, the day before yesterday it suddenly becomed successful. The JTAG could download successfully, althought I changed nothing and used the same methods before.:confused:

    Why? Maybe it will can't download later. How should I solve the problem? I think the problem has taked much time.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Yes, I faced the same problem.Just you have to be paient and keep trying that is all I can say.Restart everything that is the only solution.You will definately face it later.I face it when I dont turn off my PC for more than 4 days..

    Best Luck
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    Yes, I faced the same problem.Just you have to be paient and keep trying that is all I can say.Restart everything that is the only solution.You will definately face it later.I face it when I dont turn off my PC for more than 4 days..

    Best Luck

    --- Quote End ---

    Thank you very much for your reply!

    It seems that this error has nothing to do with the system design or my

    operation. And the solution is only to keep trying.:(

    I found that if it suddenly becomed successful and JTAG could download successfully, it would keep remain successful for a long time.

    But at the same time, if I tried another project which contained an IP core to download, it counldn't download to FPGA hardware as before...
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    I found that if it suddenly becomed successful and JTAG could download successfully, it would keep remain successful for a long time.

    But at the same time, if I tried another project which contained an IP core to download, it counldn't download to FPGA hardware as before...

    --- Quote End ---

    When you get the proper reasonable solution,please post it over here,so that others dont get panic and spend much time if getting this type of mysterious error/warning.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I just restart everything again and again... And it suddenly becomed successful. The JTAG could download successfully, althought I changed nothing and used the same methods before.

    But I don't think it is a good solustion. And as I have said before, if I tried another project which contained an IP core to download, it counldn't download to FPGA hardware as before.

    I also hope anyone can supply some better idear.