AXI4-Lite Firewall IP core - Altera support request

Greetings Altera,

Just FYI, I writing in the community forum, in addition to a sent an inquiry yesterday, through the website contacts form - https://www.altera.com/contact - in attempt to get into contact and start a conversation going with some of your FAEs regarding a problem our company and team is facing:

Currently in one of our FPGA Designs utilizing Altera FPGAs (CycloneV SoC ARM (5CSEBA5)), there is a requirement to monitor and control data streams/transfers between AXI4 master and slave devices. We have to ensure those are occurring in the allowed (configurable) address ranges, and if not, such data transfer is canceled – both downstream and upstream, the master is kept aware, and an interrupt is driven out.

A Nios II CPU shall be able to configure (access) this IP core – set these address ranges, read statuses, etc. Also it will be the recipient of the IRQ from core in case of faults.

Basically, we are looking for a simple configurable (read&write) AXI4-Lite Firewall/Pass-through/Configurable Bridge (whatever you want to call it) type of IP core – that will sit between two AXI connected type devices (master on one-side & slave on the other) and oversee the communication between them. For Altera Cyclone V SoC FPGAs.

At this point we cannot find such component from the Altera’s Quartus IP cores (Platform Designer) library. Also, it is not obvious for us how to, or, even if it is possible to ‘construct’ such device, from other IPs already available in the library ???

That’s why I am reaching to you for support on the matter. To check what approach or solution can you suggest , do you have anything available as service or ip core that could solve our problem, recommend us an IP vendor , etc...

Here's a general block diagram of what we have in mind: