Forum Discussion
New ContributorAXI4-Lite Firewall IP core - Altera support request
Greetings Altera,
Just FYI, I writing in the community forum, in addition to a sent an inquiry yesterday, through the website contacts form - https://www.altera.com/contact - in attempt to get into contact and start a conversation going with some of your FAEs regarding a problem our company and team is facing:
Currently in one of our FPGA Designs utilizing Altera FPGAs (CycloneV SoC ARM (5CSEBA5)), there is a requirement to monitor and control data streams/transfers between AXI4 master and slave devices. We have to ensure those are occurring in the allowed (configurable) address ranges, and if not, such data transfer is canceled – both downstream and upstream, the master is kept aware, and an interrupt is driven out.
A Nios II CPU shall be able to configure (access) this IP core – set these address ranges, read statuses, etc. Also it will be the recipient of the IRQ from core in case of faults.
Basically, we are looking for a simple configurable (read&write) AXI4-Lite Firewall/Pass-through/Configurable Bridge (whatever you want to call it) type of IP core – that will sit between two AXI connected type devices (master on one-side & slave on the other) and oversee the communication between them. For Altera Cyclone V SoC FPGAs.
At this point we cannot find such component from the Altera’s Quartus IP cores (Platform Designer) library. Also, it is not obvious for us how to, or, even if it is possible to ‘construct’ such device, from other IPs already available in the library ???
That’s why I am reaching to you for support on the matter. To check what approach or solution can you suggest , do you have anything available as service or ip core that could solve our problem, recommend us an IP vendor , etc...
Here's a general block diagram of what we have in mind:
(download the attached .png for better resolution)
I hope we can talk soon.
Best Regards,
- Georgi M.
2 Replies
gmWoodBGHello ShengN,
Thank you for replying to me so quickly. Yes, as mentioned I am aware that there's not such core in the Quartus IP library readily available. My inquiry is somewhat different though, I will try to break it down to separate items:
- Have you (Altera) done some design prototyping or example, etc. on this topic/problem? If so can you share this design solution (RTL or whatever) with us?
- You mentioned the built-in Platform Designer components - do you have any idea, suggestion or instruction on how to achieve the requested functionality or something close to that ? Anything that could help.
- If you can't share or nothing like this exists - is it possible to request such design or IP from you, as a paid service if need be?
- Is it possible to get some contact information (email preferably) to any of your FAEs to discuss the topic in more detail and for better clarity?
Thank you & Best Regards,
- Georgi
ShengN_alteraSuper Contributor
Hi Georgi M,
We don't have that kind of IP core. Probably need to create a custom one.
So far the closest built-in Platform Designer components are:
AXI bridges
AXI interconnects
Address span extenders
Clock crossing bridges
Protocol adapters
