Forum Discussion
Occasional ContributorAVMM transparent bridge
Occasional Contributorthank you Wincent for your reply,
I am using Agilex7 FPGA.
the AVMM master port is part of PCIe ip - and agent port at memory is intel onchip memory ip . Both are altera IP from ip catalog. the memory is mapped BAR0. in my application BAR 0 is acting as config area and based on read writes accesses to particular offsets some internal logic need to change FSM states.
for this purpose i need to a copy of all AVMM agent port signal, Once I have copy of this signals, I can write my own RTL to monitor activities interesting to us and change internal FSM states as I wish.
once the logic is developed I will need to do signal tap analysis to make sure my logic is working as intended, So your response regarding signal tap definitely helps, but I still need help on how can i get AVMM agent port signal copy so that I can write my own logic based on AVMM activities.
thanks
Regular ContributorHi ,
May I know which device that you targeted ? because for Agilex 7 we have F-tile for higher bandwidth , P-tile and R-tile for Gen5.
At the same time for Agilex 7, we only provided AVST and MCDMA IP design example. For AVMM implementation , I assume this is your own custom design right ?
About AVMM port signal information, I found some description in MCDMA user guide.
If you are asking about the naming of write and read signal
You can try to navigate it under the AVST user guide based on the tile that you are using
https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-guidance/pcie-support.html
Not sure if this is something that you looking at or not ? If not please let me know
Regards,
Wincent
- UserID4331231
I am using MCDMA R-Tile Design Examples for Endpoint. https://www.intel.com/content/www/us/en/docs/programmable/683517/22-4/mcdma-r-tile-design-examples-for-endpoint.html
in figure 2 below Mem_PIO is mapped to BAR0. in my design since BAR0 is used as config area I need to write an RTL to monitor RD/WR traffic to "MEM_PIO"; and to do that I need access to AVMM agent port`s copy.
for example
- BAR 0 offset 0x0 to 0x10h is my config area.
- Host copies "input data" at BAR0 offset 0x100h to 0x200h.
- host writes 0x1h to BAR0 offset 0x0h (part of config area) this means that data between offset 0x100h and 0x200h is valid and my design can use these input data to generate output data.
- Output data is copies to unique offset in BAR0.
as you can see at step number my RTL design need to monitor accesses to BAR0, I can only write my RTL if i have access to AVMM agent port activities. I need to know
- What BAR0 offset is accessed by host?
- is it read or write access?
- if its write what value is being written?
My RTL design can only work I have copy of all accesses. My RTL design is not trying to intercept AVMM traffic or modify AVMM request or responses by any means. Its just looking at the activities and take action for internal logic when needed.
So how do i get access to AVMM agent port?
- Wincent_Altera
Hi,
Thanks for such clear and detail clarification.
So you might need to check the AVMM agent port signal copy in order to take action for internal logic when needed.
If that is the cases, perhaps you can check on3.7. Avalon® -MM Agent Addressing
Let me know if it is not clear, And I am happy to provide better clarification on that.
Regards,Wincent
- UserID4331231
Attaching the Qsys screenshot here. This project is example design generated by quartus. there is no medication done yet.
the highlighted connection is between PIO0 IP`s PIO_master port(AVMM Host) and MEM0`s S1 port(AVMM agent)
MEM 0 is mapped to BAR 0. In your response you mention "So you might need to check the AVMM agent port signal copy"
Where can I find this option to get MEM0.S1 port copy ? can you provide me steps to find this option?
I checked in Parameters tab for Mem0 IP but dont see such option.
I also checked Parameters tab for PIO IP but dont see such option.
I reviewed the link https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/mm-agent-addressing.html which you have mentioned. I understood the address alignment information provided and find it useful in writing my own monitoring logic once I get copy of AVMM agent port signals.
thanks
- Wincent_Altera
Hi ,
You can try to export the master and slave in the top level and check the connection
re-wire the connection with the module via qsys (normally qsys will perform auto-assignation on the wire) , but you may need to check the connection well.
If you not sure how to connect it , I suggest to file a new thread , so that our Quartus Software specialist can take a look and guide you accordingly on the connection.
You can try to perform the application test and check if the read/write is working as expectation or not.
Regards,Wincent_Altera
