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JJame30's avatar
JJame30
Icon for New Contributor rankNew Contributor
6 years ago

avl_address order in uniphy ip

Hi Sir,

I am working on SEN02G64C4BH2MT-30WR DDR2. i am using uniphy ip in quartus. (Stratix 4)

I am able to do single write and read to a particular address location with specific data.

For bulk data read and write, i incremented address location and data by one, in top vhdl file (avl_addr = avl_addr +1 and avl_wdata = avl_wdata + 1). but am i missing some of data.

pll_ref_clk = 100MHz.

afi_clk = 266.66 MHz

MEM_CLK = 133.33Mhz (half rate).

Regards,

JERIN

7 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    6 years ago

    Remember that with Avalon in Platform Designer, masters, by default, use byte addressing while slaves, like the memory IP, use word addressing. You don't mention what your data width is, but if, for example, it's 32 bits, you need to increment the address by 4 on the master to get to the next 32-bit data.

    #iwork4intel

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    HI,

    sstrell has a point.

    Besides that, you also want to watch out if there is burst setting in your DDR2 avalon transaction.

    Thanks.

    Regards,

    dlim

    • JJame30's avatar
      JJame30
      Icon for New Contributor rankNew Contributor
      6 years ago

      Sir,

      My parameters are:

      avl_size , i kept as 0001

      avl_wdata = 256 bit

      mem_dq = 64 bit (half rate)

      avl_addr = 26 bit

      My initial address was X"0000000", for increasing address location by 1(X "0000001"), i want to add 4 with avl_addr ?

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    HI,

    Another thing to watch out is the DDR2 IP local_be signal, byte enable signal setting.

    Feel free to try and error to increment the avl_addr as it's unclear which path in your design is facing the issue now

    One thing to take note is you can add signal_tap to monitor your avalon bus transaction to see where thing goes wrong to figure out the issue is with your avalon master or any QSYS interconnect bridge or on your DDR2 IP avalon slave side

    Thanks.

    Regards,

    dlim

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    HI,

    Hopefully everything goes well with your issue debug

    For now, I am setting this case to closure.

    Thanks.

    Regards,

    dlim