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JJame30's avatar
JJame30
Icon for New Contributor rankNew Contributor
6 years ago

avl_address order in uniphy ip

Hi Sir, I am working on SEN02G64C4BH2MT-30WR DDR2. i am using uniphy ip in quartus. (Stratix 4) I am able to do single write and read to a particular address location with specific data. For bulk ...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

HI,

Another thing to watch out is the DDR2 IP local_be signal, byte enable signal setting.

Feel free to try and error to increment the avl_addr as it's unclear which path in your design is facing the issue now

One thing to take note is you can add signal_tap to monitor your avalon bus transaction to see where thing goes wrong to figure out the issue is with your avalon master or any QSYS interconnect bridge or on your DDR2 IP avalon slave side

Thanks.

Regards,

dlim