Avalon MM master read/write template problem

Device: DE0-Nano Cyclone IV-E EP4CE22F17

I'm still new in this stuff and I tried using the SDRAM component of the device using the Avalon MM master read/write.

During my initial testing, I was able to Write and Read data for a specific address and playing with the LED. The problem is that I wasn't able to increment the address just like I wanted to. Also, I was able to write/read but my signaltap II doesn't show the clock signal of the output of the PLL which is connected to DRAM_CLK.

My code below, Note that READ and WRITE refers to the push buttons:

reg gooff=0;
reg rboff=0;
reg init_r=1;
reg init_w=1;
reg m_read=0;
reg m_write=0;
always @(posedge CLOCK_50)
begin
    if (!READ)
    begin
        m_read <= 1;
        m_write <= 0;
    end
    
    if (!WRITE)
    begin
        m_read <= 0;
        m_write <= 1;
    end
    
    if (m_write == 1 && init_w == 1)
    begin
        reg_qsys_sdram_write_control_fixed_location <= 1;
        reg_qsys_sdram_write_control_write_base <= 0;
        reg_qsys_sdram_write_control_write_length <= 8;
        reg_qsys_sdram_write_control_go <= 1;
        
        reg_qsys_sdram_write_user_write_buffer <= 1;
        
        if (gooff == 0)
        reg_qsys_sdram_write_user_buffer_input_data <= 8'hFFFF;
        
        reg_qsys_sdram_read_user_read_buffer <= 0;
        init_w <= 0;
        init_r <= 1;
    end
    
    if (m_read == 1 && init_r == 1)
    begin
        reg_qsys_sdram_write_control_go <= 0;
      
        reg_qsys_sdram_read_control_fixed_location <= 1;
      reg_qsys_sdram_read_control_read_base <= 0;
      reg_qsys_sdram_read_control_read_length <= 8;
      reg_qsys_sdram_read_control_go <= 1;    
        
        reg_qsys_sdram_write_user_write_buffer <= 0;
        reg_qsys_sdram_write_user_buffer_input_data <= 0;
        
        reg_qsys_sdram_read_user_read_buffer <= 1;
        init_r <= 0;
        init_w <= 1;
        gooff <= 1;
    end

The attached picture shows that I was able to Read and Write successfully but as you can see, my clk_clk(50MHz) and sdram_clock_c0_clk(50MHz lead 3ns) has a value of 0 instead of a clock cycle.

http://www.alteraforum.com/forum/attachment.php?attachmentid=11046&stc=1 http://www.alteraforum.com/forum/attachment.php?attachmentid=11047&stc=1 http://www.alteraforum.com/forum/attachment.php?attachmentid=11048&stc=1 http://www.alteraforum.com/forum/attachment.php?attachmentid=11049&stc=1

Thank you!