Avalon MM Master Interface

Hi everyone,

I try to make a AvalonMM Master Controller.

I want to use this Controller to read and write to System Memory.

However, once I try to write to memory, my system hang.

Could anyone help me to check what's going on.

Thanks

Basically, what I am doing is

1 ) declare a memory space, and I set a value in it

in program (unsigned long MemSet = 100; )

2 ) I try to read the value use my IP component to read this location

in program

IOWR(MY_MM_BASE,4,(unsigned long)&MemSet); // set Location

IOWR(MY_MM_BASE,6,2); // ask my component to read this location

3 ) Report what the component get

in program(IORD(MY_MM_BASE,0))

However, I got a funny result from SignalTap see picture below

waitrequest and readdatavalid equal to 1 at the same time.

By datasheet(picture below), it shouldn't have this condition come out.

Does someone have the same issue with me before?

I got the answer why I got this result from SignalTap

The waitrequest is for Read and Write Command, not for Slave to return data.

When System receive waitquest, means the command didn't accept from slave yet.

when waitquest become 0, means command has been receive.

Therefore, the system need to wait until valid signal become 1, and get the data.

This is my program.

--- Quote Start ---

unsigned long MemSet = 100;

IOWR(MY_MM_BASE,4,(unsigned long)&MemSet);

IOWR(MY_MM_BASE,6,2);

while (1) {

IOWR(MY_MM_BASE,6,2);

printf("MemSet = %d : %d\n",MemSet,IORD(MY_MM_BASE,0));

usleep(100000);

IOWR(MY_MM_BASE,0,(unsigned long)&MemSet);

IOWR(MY_MM_BASE,1,MemSet);

IOWR(MY_MM_BASE,6,0);

}

--- Quote End ---

My System Layout

http://i54.tinypic.com/2r2n21w.jpg

Altera Avalon MM Bus Read and Write Diagram

http://i56.tinypic.com/24vpk3t.jpg

Simple Read Operation

http://i52.tinypic.com/242c1np.jpg

This is what I really catch from Signal Tap

http://i51.tinypic.com/et9xjo.jpg