Avalon MM Master Interface

The read data valid and wait request can actually be 1 at the same time, if you are doing pipelined transfers. Then the wait request is used to control the read command flow, while the read data valid controls the read result flow. The two processes in a pipeline transfer are almost independent and can happen any time.

You can simplify your interface by removing the raddatavalid signal, disabling the pipelining. Or alternatively, to do a pipeline read:

[list][*]put the read signal at 1 and wait a clock cycle

[*]put it back at 0 as soon as waitrequest is 0

[*]wait for the readdatavalid signal to be 1

[*]read the data[/list]