AVALON_MM interface of TSE

IIRC in my case the problem was that I misinterpreted the semantics of the waitrequest signal. I thought I must not start transfers when the signal is asserted while in fact you start a transfer and at the clock cycle where waitrequest is low the transfer is complete (and you can fetch the data for a read, e.g.).

Regards

flintstone

Hi,

Thanks for all of your replies...

I am simulating the system for now, using Modelsim-Altera, will be running it inside FPGA after the simulation..and I am using HDL..

The problem is solved...since I was only checking the write operation so pay less attention to the readdata and read signals and the mistake was in readdata and read signals connections :)

Now I am able to successfully read and write separately...now going to combine these in one module and lets see how it goes..

thanks

sawaak

Hi,

Again having some troubles...

I tried to read the command config register at 8'h08...got readdata of 32'h00000000, I then write 32'h0000815b to the command config, enabling LOOP_ENA, PAUSE_IGNORE, CRC_FWD, PROMIS_EN, ETH_SPEED, RX_ENA, TX_ENA bits, then I again tried to read the register but this time got only 32'h0000015b :( what happens to the LOOP_ENA bit??

Also eth_mode signal of TSE is xx, i think it should be 1 when I have already set the ETH_SPEED bit...I am simulating the system in Modelsim-Altera..

thanks

sawaak

Hi,

The problem is again solved but this time I don't know how :(..

While looking at the provided testbench, I noticed that they used 8'h02 address for command config register, I changed the register address to 8'h02 and got everything as expected, read back is OK and also eth_mode signal is also high.

But as written on TSE userguide, in chapter 4, table 4-9, command_config register address is 8'h08 but I get the correct response by using 8'h02 as done in provided testbench...may be I am doing some silly mistake but I am not able to get it, anybody have the explanation...

thanks

sawaak

Hi Daixiwen,

Thanks for the explanation, now i understand what is going on...

thanks

sawaak

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The datasheet is a bit confusing because it gives the registers address as seen from the software on a Nios II, which is an address in a 8-bit space. The address that you give to the MAC's avalon MM bus, on the other hand, is in a 32-bit space and you need to shift the address given in the datasheet by two bits before giving it to the TSE.

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Hi Daixiwen,

Would you mind give a more detailed explanation? I don't quite understand why we need to shift the address right by 2 bits when map from Nios II software address to TSE MAC on avalon MM bus. Thanks a lot!

It is confusing.

The TSE MAC Avalon-MM interface actually accepts word addresses. That is each address on that interface represents a 4-byte (32-bit) word.

However, the datasheet specified the byte address of each register. This is the address that a NIOS processor would see for each register. With byte addressing, each address represents a byte within the 4 byte word. So address 0 is register 0, address 4 is register 1, address 8 is regsiter 2 and so forth.

So when the NIOS processor actually accesses one of these registers, it sends the byte address.

But you as the software designer don't think in terms of the byte address. You think in terms of the register address because you are using the provided macros (IOWR & IORD) for accessing the registers. These macros actually take the register address that you provide and convert it to a byte address.

So this is why the datasheet is confusing. It gives the byte addresses but you really want the word or register addresses. So take each address in the datasheet and divide it by 4 (or shift right by 2) to get the register address.

Jake