Avalon bus MM address space and decoder

Hello, Intel expert,

I have a very basic question here. while I start working on a TI JESD204B project, I have to figure out how the FX3(USB module) configured the FPGA device. have a look at the attached address map, from FX3 Master will control a lot of salves through the memory map. I assume the FX3 master send out contents to a slave through the assigned space, but I have tracking the signal link from the Master write command to the slave receiver. I tried several times, but I couldn't find or figure out how the memory address on the bus was decoded and distributed.

I am pretty new to the Avalon architecture, could anyone familiar Avalon bus give me some hint, link that explain how the Avalon master and slave arrange the memory space, where the address decode happened.

Thanks

David