Forum Discussion
dsun01
Contributor
ContributorAvalon bus MM address space and decoder
Hello, Intel expert,
I have a very basic question here. while I start working on a TI JESD204B project, I have to figure out how the FX3(USB module) configured the FPGA device. have a look at the ...
sstrell
Super Contributor
Super ContributorI'm not sure what your question actually is, but the host (master) issues read and write commands to the Platform Designer interconnect, which then sends them to the appropriate agent (slave) address location. All of these agents are in the host's address space.
The Avalon spec is here: https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/manual/mnl_avalon_spec.pdf
