Avalon bus MM address space and decoder

I'm not sure what your question actually is, but the host (master) issues read and write commands to the Platform Designer interconnect, which then sends them to the appropriate agent (slave) address location. All of these agents are in the host's address space.

The Avalon spec is here: https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/manual/mnl_avalon_spec.pdf