ATX PLL profile reconfiguration

Hi,

From your issue description, could the issue be related to multiple JTAG source design is trying to access ATX PLL reconfig bus causing bus congestion and hence reconfig failure ?

You may want to review your reconfig bus connection again and make sure you are accessing the correct reconfig address space.

I would recommend you to start with sim verification for your actual design that doesn't use system console.

You can also refer to below example link to cross check with your own design

• https://community.intel.com/t5/FPGA-Wiki/Arria10-Transceiver-PHY-Basic-Design-Examples/ta-p/735196

Thanks.

Regards,

dlim