iiwan
New Contributor
New ContributorATX PLL profile reconfiguration
I need in my design for Arria 10 to reconfigure ATX PLL with 3 profiles, 1250,2500,5000 MHz output clock. Configured profiles, enabled embedded streamer and everything other needed as in xcvr user guide.
Also I added jtag_to_avalon_master_bridge. Connected with reconfiguration pins of ATX PLL. And reconfiguration via system console does work. Profiles does not change.
But if I remove jtagtoavalonMB and add internal jtag debug master in ATX PLL reconfiguration with profiles works good. At the end of test I will use my own logic with reconfiguration, not with system console.And my own logic does not work too.
I could not find problem and need help. May be after reconfiguration I have to send mgmt_reset of reconfiguration? Or something not mentioned in documentation?
Also I added jtag_to_avalon_master_bridge. Connected with reconfiguration pins of ATX PLL. And reconfiguration via system console does work. Profiles does not change.
But if I remove jtagtoavalonMB and add internal jtag debug master in ATX PLL reconfiguration with profiles works good. At the end of test I will use my own logic with reconfiguration, not with system console.And my own logic does not work too.
I could not find problem and need help. May be after reconfiguration I have to send mgmt_reset of reconfiguration? Or something not mentioned in documentation?
