New ContributorArria10 LVDS SerDes Tx/Rx loopback question
Hi,
I'm trying to implement altera_lvds IP core in Arria10 device, and using modelsim to check behavior before implementing to hardware. The target is establishing a simple loopback function with following setup:
- Quartus version: Prime Pro 18.1
- ALTLVDS_Tx IP-Core
- Funtion Mode: Tx
- Number of channel: 2
- Data Rate: 600Mbps
- SerDes Factor: 6
- PLL Setting: Internal PLL, inclock=100MHz
- Tx core register is clocked by "tx_coreclock"
- Desired tx_outclock phase shift: 0 degree
- Tx_outclock division factor: 6
- ALTLVDS_Rx IP-core
- Functional Mode: Rx Non-DPA
- Number of channel: 2
- Data Rate: 600 Mbps
- SerDes Factor: 6
- PLL setting: Internal, inclock=100MHz
- Desired receiver inclock phase shift: 0 degree
In quaruts project, I've initiated these two instance and connect tx_out[1:0]/tx_outclock of ALTLVDS_Tx to rx_in[1:0]/rx_inclock of ALTLVDS_Rx accordingly in modelsim testbench, so I should be able to see loopback parallel data from rx_out[11:0] port of ALTLVDS_Rx.
However, the waveform in modelsim wasn't exactly the same as what I expected. I have a "0° Edge Aligned tx_outclock x6 Serializer Waveform with Division Factor of 6 " in modelsim, which is incidental as user guide described. (page 20, figure 7, https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_lvds.pdf)
Here in ALTLVDS_Tx I have a fixed 12 bit value 0xBCD for test. In above waveform, we can see 0xBCD is decomposed into 2 serial data lane within a tx_outclock cycle.
In the ALTLVDS_Rx side, the inclock and data phase relationship is intact and remains "0° Edge-Aligned inclock x6 Deserializer Waveform with Single Rate Clock", similar as waveform in user guide below:
But somehow the rx_out[11:0] I got is not the fixed value I sent in ALTLVDS_Tx side. looks like there's bit shift occurs within ALTLVDS_Rx core. What makes me confused is, I though my case should be the simplest scenario of LVDS IP-core loopback, but not working. The inclock of Rx side is the "frame clock" of data, by using this as Rx internal PLL reference, it should work as word aligner and user doesn't need to do any bitslip or link training logic.
Plus, by checking modelsim waveform, the behavior doesn't matched with Figure 3 in user guide. If I follow Figure 3's logic, I got totally different output result of rx_out[11:0].
I've tried to tune "Desired receiver inclock phase shift" value of ALTLVDS_Rx IP core, and it did effect the rx_out[11:0] value, but still I can't have correct pattern I expected.
Could Intel support team have advice?
Thanks
