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Frequent ContributorJune 12, 2020 at 12:18 PM
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Thanks Alex. Do let us know if you need further help on this topic.
Eng Wei
Alex Huang (Customer)
June 12, 2020 at 12:07 PM
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Hi Wei,
No worries, I can try to build a HDL for bitslip with reference doc.
Thanks again for your support, I believe you can close this case now
Alex
June 12, 2020 at 12:00 PM
Hi Alex
Unfortunately I can't find any design example from my side. But the explanation on the bitslip requirement seems accurate here where I used it in my testbench.
Section 5.6.5.1.3. Data Realignment Block (Bit Slip)
https://www.intel.com/content/www/us/en/programmable/documentation/sam1403483633377.html#sam1403482391636
For actual usage, we can create a comparison logic to enable bitslip until it locked to the correct pattern before we start accepting functional Rx input.
I can work with you on the design but I personally more comfortable with verilog coding instead of VHDL.
Thanks.
Eng Wei
Alex Huang (Customer)
June 11, 2020 at 7:16 AM
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Hi Wei,
Got it. It's good to know that we'd better to have Rx block trained before use it. Does Intel has any reference/example design regarding link training by any chance?
Thanks,
Alex
Open Eng Wei Oh Preview
June 10, 2020 at 6:45 PM
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Hi Alex
It is recommended to perform bit alignment with training pattern before putting the Rx block into functional. The good thing of the test pattern is that we can do delay on a per channel basis to confirm that all the channels are functional.
Thanks.
Eng Wei
Alex Huang (Customer)
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Hi Wei,
No worries, thanks for your time.
And yes, looks like bitslip is way to go. But it confused me since currently I'm doing simulation in modelsim only, I thought the result I got should be an "ideal" one, no need to add extra bitslip effort on it. Like you said, mostly this feature is used for channel-to-channel skew.
Could you help me out to clarify my concept?
Thanks
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Hi Alex
I am sorry for delaying the response as I am trying to understand your design, reproduce the issue and figuring the solution for it after long holidays.
I am implementing the similar design with similar tx's input. At the rx side, I am adding 2 bitslip pulses to realign the bits accordingly.
The 2 pulses is aligning the 6 MSB and 6 LSB accordingly, from 111110_110100 -> 011111_011010 -> 101111_001101.
Bitslip is used to compensate for this channel-to-channel skew and establish the correct received word boundary at each channel. For more information, we can refer to https://www.intel.com/content/www/us/en/programmable/documentation/sam1403483633377.html#sam1403482391636
Thanks.
Eng Wei
