New Contributor
New ContributorHi Wincent,
After a rough reading on PCIe LTSSM transition rules today. I assume a desired speed change (upgrading) on LTSSM should be:
L0 -> Recovery.Rcvlock -> Recovery.Rcvconfig -> Recovery.Speed -> Recovery.Rcvlock (at higher PHY rates) -> Recovery.Rcvlock -> Recovery.Rcvconfig -> Recovery.Idle -> L0
Please kindly confirm if this is correct.
So the main problem here is that LTSSM enters Recovery.Idle rather than Recovery.Speed, after Recovery.Rcvconfig. And according to my research, PCIe spec has defined possible reasons. Clearly, it should be a negotiation failure on TS2, rather than SI issues, because we are still on Gen1 data rates.
Page 291 of PCI Express Base Spec Rev 3.0
I'm also using SoftDFE and SoftPolarityInv fixups, as they are documented to address compatibility problem in a open system. In Soft Polarity Inversion fixup, it mentioned that TS2 Ordered Set may not be received correctly during the Polling.Config state. Another question here, does that affects the speed negotiation?
Furtherly, because Soft Polarity Inversion is enabled and the IP is plain text. And it demonstrates the usage of test_out interface. I plan to extract TS2 raw data from test_out PIPE interface. Let's see if it work out.
Regular ContributorAfter a rough reading on PCIe LTSSM transition rules today. I assume a desired speed change (upgrading) on LTSSM should be:
L0 -> Recovery.Rcvlock -> Recovery.Rcvconfig -> Recovery.Speed -> Recovery.Rcvlock (at higher PHY rates) -> Recovery.Rcvlock -> Recovery.Rcvconfig -> Recovery.Idle -> L0
Please kindly confirm if this is correct.
>> About PCIe link training state machine you can refer below
>> https://www.oreilly.com/library/view/pci-express-system/0321156307/0321156307_ch14lev1sec6.html
So the main problem here is that LTSSM enters Recovery.Idle rather than Recovery.Speed, after Recovery.Rcvconfig. And according to my research, PCIe spec has defined possible reasons. Clearly, it should be a negotiation failure on TS2, rather than SI issues, because we are still on Gen1 data rates. Page 291 of PCI Express Base Spec Rev 3.0
I'm also using SoftDFE and SoftPolarityInv fixups, as they are documented to address compatibility problem in a open system. In Soft Polarity Inversion fixup, it mentioned that TS2 Ordered Set may not be received correctly during the Polling.Config state. Another question here, does that affects the speed negotiation? Furtherly, because Soft Polarity Inversion is enabled and the IP is plain text. And it demonstrates the usage of test_out interface. I plan to extract TS2 raw data from test_out PIPE interface. Let's see if it work out.
>> Okay, I see you are referring to the correct PCie base spec, let me know if there is anything I could help you to move forward.
>> But for debugging ltssm stucking in certain stage , I do recommend you to check below guide, it might give you some of the hint to move forward.
>> https://community.intel.com/t5/FPGA-Wiki/FTA-PCI-express/ta-p/735993
Regards,
Wincent
