Arria 10 PCIe DMA Bus Mastering

I am not looking for an interrupt design, however I will be utilizing interrupts in the design I am asking about.

Background:

Previously we had a board using an Intel Cyclone IV FPGA. It utilized 6 bars and 2 direct DMA channels. My current design has the BARs and we are testing them currently. The next task is to instantiate these direct DMA channels.

The way the Endpoint-to-Host-PC channel works:

The host PC utilizes a BAR to write a host memory address space which has been mapped and is free to be used by the endpoint. To be clear this is an address in Host PC memory. The endpoint FPGA board then writes to this address space and triggers an interrupt when finished. The host PC then knows to read from the address space and we repeat. This process has been described to me as Bus Mastering. The key point is that the Endpoint FPGA Board is writing to Host PC memory and it is not done through a BAR.

Question :

How do I achieve this design?