Hi,
Doing a BAR read/write is different from doing an interrupt.
When FPGA PCIe is an endpoint, the host written data to a BAR will be sent to on-chip memory. This data transfer requires help from a driver.
If you're looking for an interrupt design, you may check
1. Implementing MSI-X for PCI Express in Altera FPGA Devices - Intel Community
2. https://www.intel.com/content/www/us/en/docs/programmable/683686/20-4/setting-up-and-verifying-msi-interrupts.html
3. https://www.rocketboards.org/foswiki/Projects/A10AVCVPCIeRootPortWithMSILTS
The 1st one is more conceptual, only sim.
The 2nd and 3rd ones are more practical.
Regards,
Rong
Occasional Contributor
