Forum Discussion
Aflop
Occasional Contributor
Occasional ContributorArria 10 PCIe DMA Bus Mastering
Background: I have been working with the Arria 10 GX Devkit and using the PCIe with DMA HIP. I have the general scheme working with 5 BARs of memory with a few minor kinks. Problem : In addition ...
RongY_altera
Contributor
ContributorHi,
Doing a BAR read/write is different from doing an interrupt.
When FPGA PCIe is an endpoint, the host written data to a BAR will be sent to on-chip memory. This data transfer requires help from a driver.
If you're looking for an interrupt design, you may check
1. Implementing MSI-X for PCI Express in Altera FPGA Devices - Intel Community
3. https://www.rocketboards.org/foswiki/Projects/A10AVCVPCIeRootPortWithMSILTS
The 1st one is more conceptual, only sim.
The 2nd and 3rd ones are more practical.
Regards,
Rong
