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MIT_R_D's avatar
MIT_R_D
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Arria 10: Native Phy CDR in Manual Mode LTD

Transceiver Mode: RX Simplex
CDR: Manual Mode LTD
Data Rate 10000 Mbps

In this above setting, if RX receive two different data rate which we can use same reference CDR clock, whether Rx can decode the data without changing data rate(we will keep higher data rate(10G)) or not?

Example
CDR Reference clock: 200MHz
Data Rate: 10G, 8G

3 Replies

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor

    Hi,


    You can use same CDR refclk frequency for different data rate if it's within supported range in NativePHY IP drop down selection.


    However, one CDR setting is meant to lock to one data rate only.

    • For instance, your default setting is10G with certain CDR refclk frequency setting


    If you plans to run the transceiver channel in 8G later then you need to re-configure the NativePHY IP with 8G IP setting


    You can't send 8G data transfer to NativePHY IP with 10G setting.


    Recommended approach is you should have 2 reconfigure profile in NativePHY IP

    • one 10G profile and another 8G profie
    • You can switch the profile via reconfiguration process in real runtime depends on your system is sending 10G or 8G data


    Thanks.


    Regards,

    dlim



  • MIT_R_D's avatar
    MIT_R_D
    Icon for Occasional Contributor rankOccasional Contributor

    @Deshi_Intel

    Thanks for your response.

    I am littlie confused about CDR at10G Manual Mode LTD and CDR at 10G Automode

    When receiver receive other than 10G rate what will be rxdata and rx_clk in both case?

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor

    HI,


    Pls see my reply below


    1. I am littlie confused about CDR at10G Manual Mode LTD and CDR at 10G Automode
    1. When receiver receive other than 10G rate what will be rxdata and rx_clk in both case?
    • I don't understand your question as the both rxdata and rx_clk is incoming data transfer from external system to FPGA transceiver Rx channel
      • You should understand what your system is sending to FPGA Rx channel, right ?
      • From FPGA Rx channel side, below is the expectation example
        • If NativePHY is configured to 10G setting and incoming Rx data transfer is 10G with no signal integrity concern, then CDR should locked
        • If NativePHY is configured to 10G setting and incoming Rx data transfer is 8G, then CDR will likely loose lock as this is not expected data transfer that match with 10G setting


    Thanks.


    Regards,

    dlim